Peter Nunan General Manager Display Yield Technology Group Applied Materials
Title: A Parallel Yield Universe Applying inline eBeam tools to Accelerate Yield Learning
Abstract: Applied Materials, IncA look back at how the semiconductor industry introduced eBeam technology to enable Moore’s law and how AKT is applying semiconductor SEM yield techniques to accelerate display yield learning.
Humans have always craved information and it has been the sharing of information which has driven the advances in every scientific branch. All human endeavors have improved exponentially tied to the speed at which information can be shared. Traditionally, information was difficult to share and was transmitted via letter carrying couriers and took months to span oceans. Once man entered the electronic age with the telegraph and Alexander Graham Bell’s telephone, information could be shared instantly. With the invention of the transistor by Shockley, Bardeen and Brattain1in 1947 at Bell Laboratories, followed by the invention of the integrated circuit by co-inventors Jack Kilby of TI and Robert Noyce of Fairchild Semiconductor, the information age became truly turbocharged2. The pace of change in the semiconductor industry has been driven by Moore’s law, the observation by Intel cofounder Gordon Moore that the number of transistors in a dense integrated circuit doubles about every two years3.
This doubling of transistors every two years brought about big challenges in device scaling and especially the ability to “yield” the ever increasingly complex integrated circuits. Until the mid ‘80s, if an engineer wanted to observe or measure integrated circuit killing defects under a Scanning Electron Microscope, the silicon wafer on which the IC was fabricated need to be “broken”. In 1984, Hitachi followed rapidly by other suppliers introduced the first “full wafer SEM” making it possible to make sub-µ measurements and analyze in process defects without “breaking the wafer”. In the mid 80’s, IC manufacturers were working on 200mm wafers. Building a vacuum chamber and stage to accommodate 200mm wafers was initially challenging but became common place by the mid 90’s. Full wafer SEMs have enabled all Semiconductor process tools to evaluate improvements, which in turn enabled Moore’s Law. Following the Semi Playbook, AKT has introduced “Full Substrate” SEMs for all display generations from Gen 6 1.5Mx1.85M to Gen 11, 2.94M x 3.37M sized substrates. The Gen 6 & Gen 11 Substrates are ~40 and 140 times the size of today’s 300mm Silicon Wafer respectively!
In this presentation the author will share examples and methods by which full substrate display SEMs are being applied to accelerate the yield learning rate of the display industry and thereby greatly lower manufacturing costs.
1 "The Nobel Prize in Physics 1956". Nobelprize.org 2MINIATURE SEMICONDUCTOR INTEGRATED CIRCUIT Filed May 6. 1959 J. s. KILBY 3,115,581 Dec. 24, 1963 J. s. KILBY 3,115,581 3Gordon E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics, pp. 114–117, April 19, 1965
Bio: Peter D. Nunan is the General Manager of Applied Materials Display Yield Technology Group. He joined Applied Display Group in 2014 with the stated objective of bringing Semiconductor yield methods and equipment to the display industry. YTG’s goal is to enable display manufacturers to develop and produce advanced displays. Prior to joining Applied Display Group, Peter held various positions within the semiconductor industry. Recent Positions are: VP of Varian Semiconductor Technology Development, VP-GM of KLA-Tencor’s Professional Services Division.
Peter holds a Bachelor of Science degree in Engineering Physics and a Master of Science in Electrical Engineering from Lehigh University.